The minimum feature sizes of integrated circuits (ICs) have been shrinking for years. Commensurate with this size reduction, various process limitations have made IC fabrication more difficult. One area of fabrication technology in which such limitations have appeared is photolithography. Photolithography Involves selectively exposing regions of a resist coated silicon wafer to a radiation pattern, and then developing the exposed resist in order to selectively protect regions of wafer layers.
An integral component of a photolithographic apparatus is a “reticle” which includes a pattern corresponding to features at one layer in an IC design. The reticle typically includes a transparent glass plate covered with a patterned light blocking material such as chromium. The reticle is placed between a radiation source producing radiation of a pre-selected wavelength and a focusing lens which may form part of a “stepper” apparatus. Placed beneath the stepper is a resist covered silicon wafer. When the radiation from the radiation source is directed onto the reticle, light passes through the glass (regions not having chromium patterns) and projects onto the resist covered silicon wafer. In this manner, an image of the reticle is transferred to the resist.
As light passes through the reticle, it is refracted and scattered by the chromium edges. This causes the projected image to exhibit some rounding and other optical distortion. While such effects pose relatively little difficulty in layouts with large feature sizes (e.g., layouts with critical dimensions above about 1 micron), they cannot be ignored in layouts having features smaller than about 1 micron. The problems become especially pronounced in IC designs having feature sizes near the wavelength of light used in the photolithographic process.
To remedy this problem, a reticle correction technique known as optical proximity correction (OPC) has been developed. Optical proximity correction involves adding dark regions to and/or subtracting dark regions from a reticle design at locations chosen to overcome the distorting effects of diffraction and scattering. Typically, OPC is performed on a digital representation of a desired IC pattern. First, the digital pattern is evaluated with software to identify regions where optical distortion will result. Then the optical proximity correction is applied to compensate for the distortion. The resulting pattern is ultimately transferred to the reticle glass.
OPC, as now practiced, involves modifying a digital representation of a reticle design. The modification is performed by a computer such as workstation having appropriate software for performing OPC. Points separated by less than the critical dimension on the design are evaluated in sequence and corrected as necessary. Evaluation of each point requires analysis of surrounding features in two-dimensions to determine whether problematic diffraction effects are likely. If so, an appropriate correction (serif or segment removal, for example) is performed.
A problem with using OPC when performing a full mask design correction is that a substantial commitment must be made in terms of time and computing power in order to optically correct the integrated circuit design. For example, a moderately complex integrated circuit design may require at least a few days to correct with OPC even when the OPC algorithm runs on the fastest modern workstations.
The computational expense of OPC can be understood by recognizing that the correction often involves adding multiple small serifs to corners of design features and removing from, adding to, or displacing lateral sections of lines. The modifications are made only after evaluating an initial pattern with very fine granularity—typically evaluating potential correction points separated by no more than about 0.02 micrometers (using a 0.25 micron critical dimension technology). Note that a typical reticle design may include about 50-100 million “rectangles” of average size 0.5 by 0.5 micrometers. The features in and surrounding each rectangle must be evaluated in two dimensions. This process is very time consuming and requires significant computational resources because enormous amounts of data must be evaluated in order to perform OPC on a single IC chip.
Accordingly, what is needed is a system and method for efficiently and accurately performing OPC on an IC chip. The present invention addresses such a need.